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store two bits of information delivering a very cost effective high density Flash mem-
ory. The AT45CS1282 supports RapidS serial interface and Rapid8 8-bit interface.
RapidS serial interface is SPI compatible for frequencies up to 33 MHz. The dual-inter-
face allows a dedicated serial interface to be connected to a DSP and a dedicated 8-bit
interface to be connected to a microcontroller or vice versa. However, the use of either
interface is purely optional. Its 138,412,032 bits of memory are organized as 16,384
pages of 1,056 bytes each. In addition to the 132-megabit main memory, the
AT45CS1282 also contains two SRAM buffers of 1,056 bytes each. The buffers allow
the receiving of data while a page in the main Memory is being reprogrammed, as well
as writing a continuous data stream. Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses either a RapidS serial interface or a 8-bit Rapid8 interface to sequentially access
its data. The simple sequential access dramatically reduces active pin count, facilitates
hardware layout, increases system reliability, minimizes switching noise, and reduces
package size. The device is optimized for use in many commercial applications where
high-density, low-pin count, low-voltage and low-power are essential. The device oper-
ates at clock frequencies up to 50 MHz with a typical active read current consumption of
10 mA.
To allow for simple in-system reprogrammability, the AT45CS1282 does not require
high input voltages for programming. The device operates from a single power supply,
2.7V to 3.6V, for both the program and read operations. The AT45CS1282 is enabled
through the chip select pin (CS) and accessed via a three-wire interface consisting of
the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), or an 8-bit interface
consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK).
All programming and erase cycles are self-timed.
Block Diagram
WP
PAGE (1056 BYTES)
FLASH MEMORY ARRAY
SCK/CLK
CS
RESET
VCC
GND
BUFFER 1 (1056 BYTES)
I/O INTERFACE
BUFFER 2 (1056 BYTES)
RDY/BUSY
SI
SO
I/O7 - I/O0
SER/BYTE
Memory Array
To provide optimal flexibility, the memory array of the AT45CS1282 is divided into two
levels of granularity comprising of sectors, and pages. The “Memory Architecture Dia-
gram ” illustrates the breakdown of each level and details the number of pages per
sector. All program operations to the DataFlash occur on a page by page basis. The
erase operations is performed at the sector level.
2
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
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